this post was submitted on 21 Aug 2026
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Japan tried to build an operating system for the entire world, then the US government intervened (www.xda-developers.com)
submitted 5 days ago* (last edited 5 days ago) by inari@piefed.zip to c/technology@lemmy.world
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[–] greyscale@lemmy.grey.ooo 50 points 5 days ago (19 children)

PS3 comes to mind

Though in embedded, thats fairly normal.

I've got a $1 linux embedded SoC that has a 64 bit riscv core, a 32 bit riscv core for running realtime stuff and a low power embedded 6502 on it too because why not.

[–] testaccount789@sh.itjust.works 12 points 5 days ago (3 children)

Yeah, RP2350 in Raspberry Pi Pico 2 also has 2 ARM cores and 2 RISC-V cores.

Which reminds me, I purchased one a month ago to play around with as it has good documentation, yet I haven't used it once so far.

[–] greyscale@lemmy.grey.ooo 7 points 5 days ago* (last edited 5 days ago) (2 children)

Its actually not seperate cores, they're RISCV or ARM, based on a switch. MilkV does that too with one of its chips. They're mostly the same architecturally, theres something like 10% that gets enabled/disabled with each ISA selection.

[–] testaccount789@sh.itjust.works 9 points 5 days ago* (last edited 5 days ago) (1 children)

But you can still run both at once. RP2350 datasheet

From section 3.9 Arm/RISC-V architecture switching:

There are two processor sockets on RP2350, referred to as core 0 and core 1 throughout this document. Each socket can be occupied either by a Cortex-M33 processor (implementing the Armv8-M Main architecture, plus extensions) or by a Hazard3 processor (implementing the RV32IMAC architecture, plus extensions).

From section 3.9.2. Mixed architecture combinations:

The ARCHSEL register has one bit for each processor socket, so it is possible to request mixed combinations of Arm and RISC-V processors: either Arm core 0 and RISC-V core 1, or RISC-V core 0 and Arm core 1.

Practical applications for this are limited, since this requires two separate program images. The two cores interoperate normally, including shared exclusives via the global monitor: a shared variable can be safely, concurrently accessed by an Arm processor performing ldrex, strex instructions and a RISC-V processor performing amoadd.w instructions, for example

[–] greyscale@lemmy.grey.ooo 1 points 4 days ago

My point it isn't 2x arm and 2x riscv. They recycle most of the silicon used.

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